Non-volatile memory (NVM) cells, such as those used in erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories, generally may have one single chargeable area.
Another type of non-volatile cell, called a nitride, read only memory (NROM) cell, may have two separated and separately chargeable areas, each defining one bit. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The ONO stack may overlie a channel situated between a pair of bit lines. In order to program a bit, channel hot electrons (CHE) are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required.
Erasing a bit is generally accomplished by the application of a negative gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of erasing required. Different types of erasing mechanisms may be used to erase bits in NROM cells. One technique is hot hole injection, described for example in U.S. Pat. No. 6,348,711, the disclosure of which is incorporated herein by reference. In this technique, application of an erase voltage to a bit line may create holes by band-to-band tunneling in the junction of the bit line with the channel. A lateral field in the area of the junction surface may accelerate the holes such that they become hot holes. A vertical field generated by the negative gate voltage then pulls the hot holes into the nitride layer.
Charge injection, whether CHE injection or hot hole injection, must be controlled to insure proper device operation. In general, step and verify algorithms are implemented, wherein charge is injected at a certain bias (voltage level) followed by a verify operation to ascertain whether the bit has reached a desired voltage level (e.g., program verify or erase verify voltage level). If the desired voltage verify level has not been achieved, stronger charge injection may be initiated via a higher bias and vice versa.
However, in tunneling-enhanced hot hole injection, the other junction in the transistor, to which holes are not injected, should remain unbiased as possible, in order to prevent possible “punch through”, i.e., contact of the two junction depletion regions, which may slow down the charge injection process, due to the decrease of the junction lateral field. Thus, in NROM cells that comprise two physical bits per cell, and which incorporate a tunneling-enhanced hot hole injection mechanism, hole injection may not be performed simultaneously on both sides of the memory cell. This prolongs the time it takes to carry out the injection operation, and the time is prolonged even more by the step and verify algorithms. It would thus be desirable to reduce the time needed to perform the injection operation.
One option to enhance the hole injection flow may involve using relatively large voltage increments between consecutive steps of the step and verify algorithm. However, the large voltage increments may result in bad control over the injection process.
Another solution involves applying relatively large voltage increments between initial steps of the step and verify algorithm for many cells in parallel, until a first cell or selected group of cells reaches a target. The rest of the memory array is then programmed/erased with smaller increments until the full array is done.
Yet another technique samples a small amount of cells in the array to determine their behavior characteristics upon the application of pulses to program or erase. After learning how the threshold voltage changes in accordance with the pulses, the rest of the array may be programmed (or erased) en masse with a significantly reduced number of pulses and verifies.
Still another method employs multiple verify levels in an effort to obtain a faster convergence to the final pulse level. However, this method may require a more intricate design and a longer verify time.
In all of the prior art methods, each programming/erasing step is performed on both the right and left side of the memory cells. Accordingly, the basic time penalty of having to finish one side before applying pulses to the other side has not yet been circumvented.